FSC system anomalies

I found mismatch during the test FSC logic. I prepared several FLD pages for test. All FLDs work in FSC like in my program. But results  following FLD test were a big unexpectedness for me (See drawing and time diagrams. All diagrams is based on FSC SOE records)

Most people can say - backward line is the reason of this mistake. But following FLD work properly (see drawing and time diagrams). Flip-flop was shift to right. 

The reason is wrong sequence of execution. The program code for flip-flop had executed before second "AND" gate. Anybody know why it happens?
I think this is not a single incident! It is dangerous. FSC programmers must change algorithm or create special tools for test existing logic.

You can download here wrong code block for test. I had executed tests on FSC system release 5xx.

If you know any mistake in FSC system please send me description to the following address
mailto:dws_support@mail.ru